1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly to the design of a memory interface that receives data and a clock signal from a memory during a read operation.
2. Related Art
As processor speed continually increase, memory systems are under increasing pressure to provide data at faster rates. This has recently led to the development of new memory system designs. Memory latencies have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream. Such memory chips, with clocked interfaces are known as synchronous random access memories.
Recently, standards such as Rambus and SyncLink have been developed to govern the transfer of data between memory and processor using such clocked interfaces. SyncLink, which will be known as IEEE Standard 1596.7, specifies an architecture that supports a 64 M-bit memory with a data transfer rate of 1.6 gigabytes per second. SyncLink packetizes and pipelines the address, command and timing signals, and adds features that significantly increase data bus speed, thereby providing fast memory accesses without losing the ability to move quickly from row to row or to obtain bursts of data.
During read operations, synchronous random access memories return a data clock signal along with the data; this data clock signal is used to clock the data into the processor (or into a memory controller attached to the processor). This feature is a significant difference from conventional memory systems, which rely on the system clock to receive data during read operations.
Designing an interface that receives a high-speed data clock from a synchronous random access memory during a read operation presents challenges because at some point data returned during a read operation must be transferred from the high speed data clock domain into the slower speed system clock domain. This is hard to accomplish because the slower speed circuitry must somehow be able to match the data transfer rate of the high-speed circuitry. Additionally, the slower speed circuitry typically requires more setup and hold time for memory elements than is provided by the high-speed circuitry.
What is needed is a system that receives data along with an associated high-speed clock from a memory during a read operation, and that transfers this data into circuitry that is clocked by a slower system clock.